The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. With decreasing feature sizes, quantum mechanical tunneling (“tunneling”) leads to leakage current, i.e., current leaking out of device features (e.g., across gate oxides), which adversely affects device performance. For this reason, a thin SiO2 film, which is traditionally used as a gate oxide in metal-oxide-semiconductor field effect transistors (MOSFETs), can no longer function as an effective gate dielectric. Thus, an ultra-thin dielectric film with a high dielectric constant (“high-k dielectric”) is desirable.
To form a thin dielectric film on a substrate, a variety of deposition techniques have been developed. For example, chemical vapor deposition (CVD) has traditionally been used to form a high-k film on a substrate. In gate dielectric applications, electrically active defects should be minimized or prevented from forming at the interface between a substrate and a high-k dielectric. Thus, plasma treatment after CVD has been widely developed for enhancement of interface quality between a high-k film and a substrate. The uniformity of a high-k film on a substrate should be considered in addition. Hence, another method known as atomic layer deposition (ALD) has been developed for depositing a high-k film onto a substrate. However, further developments for forming high-k dielectrics are still needed to solve some problems of prior approaches.